基于Virtex 5的数字钟(Verilog)

Posted by Harid七月 - 24 - 2011 Leave comments

昨晚上我在GENESYS Virtex 5系FPGA开发板(Genesys Virtex®-5 FPGA 开发套件)上实现了数字钟,不过仅有时钟功能,现在不能设定时间,只能在reset后从“00:00:00”开始跑。

xilinx_virtex_5_fpga

下面是Project里的1个文件的代码,更多文件(整个Project,于Xilinx ISE 12.3 Platform)可下载:

time_occur.v:

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Contact: http://www.timepoet.com 
// Module Name:    time_occur 
//////////////////////////////////////////////////////////////////////////////////
module time_occur(
    input clk,
    input clr,
    output reg [3:0] hour_high,
    output reg [3:0] hour_low,
    output reg [3:0] min_high,
    output reg [3:0] min_low,
    output reg [3:0] sec_high,
    output reg [3:0] sec_low
    );
 
    reg [26:0] counter;
    reg enable;
 
    always @(posedge clk or posedge clr)
    begin
        if(clr==1)
        begin
            enable <= 0;
            counter <= 0;
        end
        else
        begin
            counter <= counter + 1;
            if(counter == 66666700)
            begin
                enable <= 1;
                counter <= 0;
            end
            else
                enable <= 0;
        end
    end
 
    always @(posedge clk or posedge clr)
     begin
        if(clr==1)
        begin
            hour_high <= 0;
            hour_low <= 0;
            min_high <= 0;
            min_low <= 0;
            sec_high <= 0;
            sec_low <= 0;
        end
        else
        begin
            if(enable == 1)
                if(sec_low==9)
                begin
                    if(sec_high==5)
                    begin
                        sec_low<=0;
                        sec_high<=0;
                        if(min_low==9)
                        begin
                            if(min_high==5)
                            begin
                                min_low<=0;
                                min_high<=0;
                                if(hour_low==3&&hour_high==2)
                                begin
                                    hour_high<=0;
                                    hour_low<=0;                                        
                                end
                                else if(hour_low==9)
                                begin
                                    hour_low<=0;
                                    hour_high<=hour_high+1;
                                end
                                else
                                    hour_low<=hour_low+1;
                            end
                        else
                        begin
                            min_high<=min_high+1;
                            min_low<=0;
                        end
                    end
                    else
                        min_low<=min_low+1;
                    end
                else
                begin
                    sec_low<=0;
                    sec_high<=sec_high+1;
                end
            end
            else
                sec_low<=sec_low+1;
        else
        begin
            sec_low <= sec_low;
            sec_high <= sec_high;
            min_high <= min_high;
            min_low <= min_low;
            hour_high <= hour_high;
            hour_low <= hour_low;
        end
    end        
    end
endmodule

该module是时钟产生模块,其通过一个enable脉冲信号来控制1秒的变化,因为该module的clk是66.6667MHz,所以在产生enable时计数器加至66666700。

   声明:本文采用 BY-NC-SA 协议进行授权 | 星期九
   原创文章转载请注明:转自《基于Virtex 5的数字钟(Verilog)


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