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Posts Tagged ‘锁存器’
七月 24 2011

用Xilinx ISE综合工程的时候,如果出现如下警告: WARNING:Xst:737 – Found 1-bit latch for signal <signal>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. 其大意是说生成了锁存器,而不推荐在FPGA/CPLD中使用锁存器。警告中也指出了是...

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